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9:00AM-9:15AM Welcome Remarks etc.
9:15AM-10:00AM Keynote: Antonio Gonzalez, Intel and UPC
10:00AM-10:30AM Break
10:30AM-12:00PM:
Session Title: Simulation
MPTLsim: a Simulator for x86-64 Multicore Architecture with Coherent Caches
Hui Zeng, Matt Yourst, Kanad Ghose and Dmitry Ponomarev (SUNY, Binghamton)
How to Simulate 1000 Cores
Matteo Monchiero, Jung-Ho Ahn, Ayose Falcon, Daniel Ortega, and Paolo
Faraboschi(HP Labs)
SlackSim: A Platform for Parallel Simulations of CMPs on CMPs
Jianwei Chen Murali Annavaram Michel Dubois (USC)
12:00PM-1:30PM Lunch
1:30PM-2:30PM
Session Title: Reconfiguration and Memory
Run-time Reconfigurable Cluster of Processors
Madhura Purnaprajna and Mario Porrmann (University of Paderborn)
Evaluation of the Memory Architecture for an SVP Microgrid
Chris Jesshope, Mike Lankamp, Li Zhang (University of Amsterdam)
2:30PM-3PM Break
3PM-4PM
Session Title: Physical Concerns and Physical Design
Real Time Power Estimation and Thread Scheduling via Performance Counters
Cornell
Co-optimization of Microarchitecture and Physical Design
Omid Azizi (Stanford), Aqeel Mahesri (UIUC), Sanjay Patel (UIUC), Mark
Horowitz (Stanford)
4:00PM Closing discussion
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