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My Home Page
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Assistant
Professor Center for
Reliable and High-Performance Computing Coordinated
Science Laboratory Specifically, my research interests include multi-core and multithreaded architectures, low-power and complexity-effective architectures, on-chip interconnects, compilation and OS issues for multithreaded architectures, embedded and reconfigurable architectures, etc. Current research goal is to build a truly adaptable processor that can adapt to all workload conditions and characteristics, and can therefore deliver performance and power characteristics as if it were designed for close to the best case, on average, instead of the average case, at best. We call this initive Amoebic Computing. Another research goal is to investigate how to build and use many-core (possibly hundreds of cores) processors. This involves studying both bottlenecks like interconnection and coherence, worst-case power, etc., as well as opportunities like enhancing reliability, availability, usability, etc. I am also interested in revisiting the roles of hardware and software in the computing stack, with special focus on mechanisms vs policies and what goes where (e.g., should process management and scheduling be done in hardware?). The two specific projects that we are doing in my lab (Passat Group) are 1) 1) Hardware and system support for actor-oriented (or message passing) programming and execution, and 2) design and evaluation of stochastic processor (or processors that do not always compute correctly by design). More details on both these projects soon (send us an email if you want to know details of these two flagship projects). I also have very broad potential interests. Please feel encouraged to take a shot at convincing me to work on something different that you are excited about. Email Address: rakeshk
AT illinois.edu I am looking for motivated graduate/undergraduate students. If you are a UIUC graduate/undergraduate student looking for an advisor or if you are someone interested in applying to UIUC for graduate studies, email me if you want to do research in computer architecture, reconfigurable computing, or hardware/software interface. See my research/publications pages for a sampling of my research. Please attach your CV as well.
Our ISQED-2010 paper on " Variation-Aware Speed Binning of Multi-core Processors" is going to be online soon.
Our DATE-2010 paper on " Scalable Stochastic Processors" is going to be online soon.
Our HPCA-2010 paper on " Designing Soft Architectures from the Ground Up (Or a Design Methodology to Allow Voltage/Reliability Tradeoffs in Processors)" is going to be online soon.
Our HiPEAC-2010 paper on " Low-Overhead, High-Speed Multi-core Barrier Synchronization" is going to be online soon.
Our ASPDAC-2010 paper on " Slack Redistribution for Graceful Degradation Under Voltage Overscaling" is going to be online soon.
Our MICRO-2009 paper on " Reducing Peak Power with a Table-Driven Adaptive Processor Core" is going to be online soon.
Our HiPC-2009 paper on " Three Scalable Approaches to Improving Many-core Throughput for a Given Peak Power Budget" is going to be online soon.
Our CASES-2009 paper on " Towards Scalable Reliability Frameworks for Error Prone CMPs" is going to be online soon.
Our USENIX HotPower-2009 paper on " Fluid NMR - Performing Power/Reliability Tradeoffs for Applications with Error Tolerance" is going to be online soon.
The slides from my invited talk on " To Guardband Or To Let a Thousand Errors Bloom" presented at the IOLTS panel are now online.
Our WEED-2009 paper on " Characterizing the Voltage Scaling Limitations of Razor-based Designs" is now online. Our IWLS-2009 paper on " Alleviating Voltage Scaling Limitations of Razor-based Designs" will be online soon.
Our DFM&Y-2009 paper " On Performance Binning of Multi-core Processors" will be online soon.
The slides from the spotlight talk on " Stochastic Processors" at the NSF Workshop on Science of Power Management are now online.
Our technical report on "Hardware Support for Debugging Message Passing Programs on Message Passing Architectures" is now online.
Our SELSE-5 paper on "Testing the Critical Operating Point (COP) Hypothesis using FPGA Emulation of Timing Errors in Over-scaled Soft-processors" is now online .
Use this link if you are looking for papers presented at the previous editions the Workshop on Design, Architecture, and Simulation of Chip Multiprocessors (dasCMP). Serving on the SELSE 2010, DATE 2010, DRV 2009, CASES 2009, and ICCD 2009 program committees. Please submit good papers. Served on the recent ISPASS-2009, SELSE, INTERACT-12, ISPASS-2008, and MICRO-40 program committees and the ISCA-2007 organizing committee.
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