208 Coordinated Science Laboratory
1308 West Main Street
Urbana, IL 61801
Rakesh Kumar is an Associate Professor in the Electrical and Computer Engineering Department at the University of Illinois at Urbana Champaign. His current research interests are in computer architecture, stochastic and approximate computing, low power and error resilient computer systems, and architectures for inference and machine learning.
His most significant research contributions are in the areas of multi-core architecture and design (his past research on heterogeneous multi-core architectures and conjoined-core architectures has directly influenced processor products and roadmaps from several companies), peak power management (he co-developed the first techniques for peak power management for single-core and multi-core processors), stochastic and approximate computing (he co-developed the first set of techniques for graceful voltage-reliability tradeoffs in hardware and functional
units; he also co-developed the concept of recovery-driven design), and algorith-based fault tolerance (he co-developed the first ABFT techniques targeting sparse algebra; he also led the development of several techniques to build error tolerant versions of applications) .
His research recognitions include several best paper awards and best paper award nominations, ARO Young Investigator Award, Arnold O Beckman Research Award, FAA Creative Research Award, UCSD CSE Best Dissertation Award, and an IBM PhD Fellowship. Teaching recognitions include appearance on UIUC's List of Teachers Ranked as Excellent.
Rakesh has a BS from IIT Kharagpur and a PhD from University of California at San Diego.
Stochastic and Approximate Computing
Energy-efficient Inference and Machine Learning
Resilient Memory Systems
Low Power, Low Storage Overhead Chipkill Correct via Multi-Line Error Correction (Multi-ECC), SC 2013, (PDF).
On Reconfiguration-Oriented Approximate Adder Design and Its Application,ICCAD 2013, (PDF).
An Algorithmic Approach to Error Localization and Partial Recomputation for Low-Overhead Fault Tolerance on Parallel Systems, DSN 2013, (PDF).
Adaptive Reliability Chipkill Correct (ARCC), HPCA 2013, (PDF).
On Logic Synthesis for Timing Speculation, ICCAD 2012, (PDF).
Algorithmic Approaches to Low Overhead Fault Detection for Sparse Linear Algebra, DSN 2012, (PDF).
Compiling for Energy Efficiency on Timing Speculative Processors, DAC 2012, (PDF).
On Software Design for Stochastic Processors, DAC 2012, (PDF). (invited)
Power-Balanced Pipelines, HPCA 2012, (PDF). (Nominated for Best Paper Award)
Architecting Processors to Allow Voltage/Reliability Tradeoffs. CASES 2011. (PDF). (Best Paper Award).
On the Efficacy of NBTI Mitigation Techniques, DATE 2011, (PDF).
MOPED: Orchestrating Interprocess Message Data on CMPs, HPCA 2011, (PDF).
A Numerical Optimization-based Methodology for Application Robustification: Transforming Applications for Error Tolerance, DSN 2010, (PDF).
Recovery-driven Design: A Methodology for Power Minimization for Error Tolerant Processor Modules, DAC 2010, (PDF).
Stochastic Computation, DAC 2010, (PDF) (invited).
Scalable Stochastic Processors", DATE 2010, (PDF).
Designing Processors from the Ground Up to Allow Voltage/Reliability Tradeoffs, HPCA 2010, (PDF).
Slack Redistribution for Graceful Degradation Under Voltage Overscaling. ASPDAC 2010, (PDF).
Reducing Peak Power with a Table-Driven Adaptive Processor Core, MICRO 2009, (PDF).
Biplab Deka (Energy-efficient Inference and Machine Learning)
Henry Duwe (Stochastic and Approximate Computing)
Xun (Stevenson) Jian (Resilient Memory Systems)
Russell Jones (Near Data Processing)
Liulin Zhong (Energy-proportional memory systems)
John Sartori (First Employment: Assistant Professor, EE Department, University of Minnesota)
Joseph Sloan (First Employment: Assistant Professor, EE Department, University of Texas at Dallas)