208 Coordinated Science Laboratory
1308 West Main Street
Urbana, IL 61801
Rakesh Kumar is a Professor in the Electrical and Computer Engineering Department at the University of Illinois at Urbana Champaign with research and teaching interests in computer architecture and system-level design automation.
His research has been recognized through one ISCA Influential Paper Award, one 10 Year Retrospective Most Influential Paper (MIP) Award (ASPDAC), several best paper awards and best paper award nominations (IEEE MICRO Top Picks, ASPLOS, HPCA, CASES, SELSE, IEEE CAL),
ARO Young Investigator Award, and UCSD CSE Best Dissertation Award.
His teaching and advising have been recognized through Stanley H Pierce Faculty Award and
Ronald W Pratt Faculty Outstanding Teaching Award.
He previously served as a Co-Founder and Chief Architect at Hyperion Core, Inc, a microprocessor chip startup.
Rakesh has a BS from IIT Kharagpur and a PhD from University of California at San Diego.
Printed Computer Systems (DATE21, MICRO20, ISCA20)
Waferscale Computing (ECTC21, DAC21, HPCA19, HPCA18)
Deeply-embedded Computing (DAC21, ISCA18, MICRO17, ISCA17, ASPLOS17, HPCA17, ISLPED16, ISCA16..)
Emerging workloads and platforms (DAC20, DAC16)
I/O Architecture, Substrate Design, and Bonding Process for a Heterogeneous Dielet-Assembly based Waferscale Processor, ECTC, 2021, (PDF).[The Next Platform]
Property-driven Automatic Generation of Reduced-ISA Hardware, DAC, 2021, (PDF).
Designing a 2048-Chiplet, 14336-Core Waferscale Processor, DAC, 2021, (PDF).
Printed Stochastic Computing Neural Networks, DATE, 2021, (PDF).
Printed Machine Learning Classifiers, MICRO, 2020, (PDF). (IEEE Micro Top Picks- Honorable Mention).
Printed Microprocessors, ISCA, 2020, (PDF).
Hardware Acceleration of Graph Neural Networks, DAC, 2020, (PDF).
Design Space Exploration for Chiplet Assembly Based Processors, TVLSI, 2020, (PDF).
Architecting a waferscale processor - a GPU case study, HPCA, 2019, (PDF). [IEEE Spectrum][Fortune][Next Platform][ExtremeTech][Tom's Hardware][TechSpot][Hexus]
(also of interest: IEEE Spectrum, NYT)
Bespoke Processors for Applications with Ultra-low Area and Power Constraints, IEEE MICRO, 2018 (link).
Guaranteeing Local Differential Privacy on Ultra-low-power Systems, ISCA, 2018, (PDF).
A Case for Packageless Processors, HPCA, 2018, (PDF). [Semiconductor Engineering]
Software-based Gate-level Information Flow Security for IoT Systems, MICRO, 2017, (PDF).
Bespoke Processors for Applications with Ultra-low Area and Power Constraints, ISCA, 2017, (PDF). (IEEE Micro Top Picks).
[IEEE Spectrum][Semiconductor Engineering][Hackaday][CircleID]
Determining Application-specific Peak Power and Energy Requirements for Ultra-low-power Processors, ASPLOS, 2017, (PDF). (Best Paper Award).
Enabling Effective Module-oblivious Power Gating for Embedded Processors, HPCA, 2017, (PDF)
Understanding and Optimizing Power Consumption in Memory Networks, HPCA, 2017, (PDF)
Bit Serializing a Microprocessor for Ultra-Low-Power, ISLPED, 2016, (PDF)
Rescuing Uncorrectable Fault Patterns in On-Chip Memories Through Error Pattern Transformation, ISCA, 2016, (PDF)
(an earlier version selected as a Best Paper at SRC TECHCON 2015).
Exploiting Dynamic Timing Slack for Energy Efficiency in Ultra-Low-Power Embedded Systems, ISCA, 2016, (PDF)
Approximate Bitcoin Mining, DAC, 2016, (PDF)[ZDNet][Slashdot][EE Times][Hacker News][Security Affairs][Coin Report][CryptoCoinNews][Coin Telegraph][Brave New Coin][NewsBTC][More]
Parity Helix: Efficient Protection for Single-Dimensional Faults in
Multi-dimensional Memory Systems, HPCA 2016, (PDF).
Correction Prediction: Reducing Error Correction Latency for On-Chip Memories, HPCA 2015, (PDF).
(an earlier version selected as a Best Paper at SRC TECHCON 2014).
ECC Parity: A Technique for Efficient Memory Error Resilience for Multi-Channel Memory Systems, SC 2014, (PDF).
Software Canaries: Software-based Path Delay Fault Testing for Variation-aware Energy-efficient Design, ISLPED 2014, (PDF).
Markov Chain Algorithms: A Template for Building Future Robust Low Power Systems, Asilomar 2013, (PDF).
Low Power, Low Storage Overhead Chipkill Correct via Multi-Line Error Correction (Multi-ECC), SC 2013, (PDF)
(an earlier version selected as the Best of IEEE Computer Architecture Letters 2013).
On Reconfiguration-Oriented Approximate Adder Design and Its Application,ICCAD 2013, (PDF).
An Algorithmic Approach to Error Localization and Partial Recomputation for Low-Overhead Fault Tolerance on Parallel Systems, DSN 2013, (PDF).
Adaptive Reliability Chipkill Correct (ARCC), HPCA 2013, (PDF).
On Logic Synthesis for Timing Speculation, ICCAD 2012, (PDF).
Algorithmic Approaches to Low Overhead Fault Detection for Sparse Linear Algebra, DSN 2012, (PDF)
(an earlier version selected as a Best Paper at SRC TECHCON 2011).
Compiling for Energy Efficiency on Timing Speculative Processors, DAC 2012, (PDF).
On Software Design for Stochastic Processors, DAC 2012, (PDF). (invited)
Power-Balanced Pipelines, HPCA 2012, (PDF).
(Nominated for Best Paper Award).
Architecting Processors to Allow Voltage/Reliability Tradeoffs. CASES 2011. (PDF). (Best Paper Award).
On the Efficacy of NBTI Mitigation Techniques, DATE 2011, (PDF).
MOPED: Orchestrating Interprocess Message Data on CMPs, HPCA 2011, (PDF).
A Numerical Optimization-based Methodology for Application Robustification: Transforming Applications for Error Tolerance, DSN 2010, (PDF).[BBC]][HPCWire][IEEE Spectrum][Engineering&Technology][Slashdot]
Recovery-driven Design: A Methodology for Power Minimization for Error Tolerant Processor Modules, DAC 2010, (PDF).
Stochastic Computation, DAC 2010, (PDF) (invited).
Scalable Stochastic Processors", DATE 2010, (PDF).
Designing Processors from the Ground Up to Allow Voltage/Reliability Tradeoffs, HPCA 2010, (PDF).
Slack Redistribution for Graceful Degradation Under Voltage Overscaling. ASPDAC 2010, (PDF).
Reducing Peak Power with a Table-Driven Adaptive Processor Core, MICRO 2009, (PDF).